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RX Pipeline

RX Pipeline

Every chapter so far that mentioned “the receiving side” left the actual mechanism unopened. This part opens it: a frame landing on the wire, parsed apart layer by layer, checked against a sequence number before it is allowed to mean anything, tracked across however many packets one message actually spans, and finally placed in host memory – plus what happens when one QP’s receive path stalls without taking any other QP down with it, what happens when many QPs’ packets arrive interleaved on the same physical pipeline, and what happens when a QP resets with a packet already mid-flight through one of these stages.

RX Pipeline is a datapath, not a resource like the QP Table or the Key Table – there is nothing here to install, cache, or evict. It has no state machine of its own; a receiving QP’s behavior is gated by the state machine QP State Machine already covers. Its one piece of persistent state is per-message reassembly context, not a demand-driven cache: an address and a remaining count held open for as long as one message is in flight, then closed. And unlike TX Packet Build, which builds a packet in a single chapter, taking a packet apart and deciding whether to admit it are different enough operations here to need two.

One packet, from wire to memory – what the RX Pipeline does to one arriving packet, from parsing through PSN check and reassembly, to the hazards that can interrupt it (single-QP stalls, multi-QP arbitration, mid-transaction reset). Each step names the chapter that covers it.

Chapters

The Receive Queue Descriptor and Ring
A Send Queue entry tells hardware what to do. A Receive Queue entry tells hardware only where – no opcode, no remote address, nothing to send. This chapter is the simplest descriptor in the book, and the ring that holds it in strict, unaddressed order.
RX Packet Parse
Every check this chapter runs is ordered by cost, cheapest first – a malformed header gets rejected before a single cycle goes toward the one check that actually costs something. This is the stage that takes a frame apart, in exactly the reverse order TX Pipeline built one.
PSN Check and Out-of-Order Arrival
A packet sequence number is a transaction tag, not a timestamp – and the three-way branch it drives (matches, too low, too high) is the single gate every parsed packet has to clear before it means anything at all. This chapter is that gate, and the one place a resolved packet actually hands off to memory.
Multi-Packet Reassembly
RETH names a destination address exactly once, on a multi-packet RDMA WRITE’s first packet, and never again. Every packet after it has to land somewhere that first packet never restated – which means something has to remember, and this chapter is what that something actually holds for the RETH-seeded case specifically.
Single-QP RX Stalls
An arriving packet can pass every check this part has covered and still not be processable – not because anything is wrong with it, but because a resource it needs isn’t there yet. This chapter is what that actually does to one Queue Pair’s receive path, and what it does not do to any other.
Multi-QP RX Arbitration
The wire does not ask permission before interleaving packets from a dozen different Queue Pairs. One shared parser and one shared placement stage still have to service them in some order – the same policy question TX Pipeline asked of the transmit side, asked here of arrivals nothing chose to interleave in the first place.
Hardware-Assisted RX Dispatch Engines
The receive path has a constraint the transmit side never faces: a packet already crossed the wire before this pipeline gets a say in when it arrives. This chapter asks the same fixed-versus-programmable question TX Pipeline asked of transmit scheduling, and finds a real structural reason the honest answer may differ.
Mid-Transaction RX Reset
Mid-Transaction TX Reset closed TX Pipeline asking what becomes of a WQE caught mid-build when RESET lands. This chapter closes RX Pipeline asking the receiving side’s version of the same question – and finds it sharper, because this part’s own reassembly state can leave a partial write sitting in memory with nothing downstream aware it is incomplete.
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